1. Field of the Invention
The present invention hardens latch or bistable logic circuits against single event upset.
2. Prior Art
The problem of high energy ionizing particle induced upset, or as it is commonly called, single event upset (SEU), encompasses a large, and constantly growing body of knowledge covering the origins and properties of high energy ionizing particles and their effects upon device physics. Interest in this subject has been motivated by numerous space and defense applications. For example, SEU's are a common occurrence in small geometry devices exposed to the heavy ions and protons in the Van Allen belts, and to solar flares and galactic cosmic rays outside the earth's atmosphere.
High energy ionizing particles passing through the volume of a logic cell produces a transient charge along the ion track. The diameter of this transient charge region can be from less than 1 micron to as large as 5 or 6 microns, depending on high energy particle type and substrate doping. The free electrons produced along the ion track either recombine with the holes in the substrate, or, if the track passes through a p-n junction they will collect to produce a transient current spike. The high density of these charge carriers can significantly influence charge carrier distribution in the junction for the duration of this spike. Depending on ionizing particle type and substrate doping, these current spikes can reach magnitudes up to 1000 microamps and durations of up to 1 or 2 nanoseconds. Clearly, they can cause the critical charge of a back-biased logic junction to be exceeded, which in turn can change the state of a bistable logic element. Such errors have been observed in space vehicle applications of RAMs, microprocessors, PROMs and logic devices. While some permanent failures have been reported, possibly due to latch-up in certain devices, the majority of faults are "soft," i.e., a logic state change occurs without permanent damage.
The SEU problem is becoming increasingly important as chip designs approach submicron feature sizes. For example, bipolar logic circuits in this region operate with collector currents on the order of 1 microamp, and clock rates on the order of 50 to 100 megahertz. Since the current spikes generated by heavy high energy particles can reach levels up to 1000 microamps and pulse widths of up to 1 or 2 nanoseconds, they are directly within the response range of these bipolar logic circuits which may be clocked in normal operation by pulse width of less than 5 nanoseconds.
CMOS/SOS technology is inherently less sensitive to the currents generated by high energy ionizing particles. However, computer simulations with postulated parameters at submicron feature sizes also indicate logic state changes when critical junctions are subjected to 1000 microampere pulses of 1 nanosecond duration. In fact, as feature size decreases the CMOS/SOS and bipolar technologies tend to display comparable sensitivities.
Achievement of hardened circuits, therefore, appears virtually impossible at first glance. However, a novel circuit configuration has been devised, which provides the necessary hardness by virtue of its functional arrangement (local redundancy) and isolation protection and is independent of device technology.